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ahb_slave
- 异步memory ahb lite slave接口verilog代码-verilog code of ahb lite slave for memory interface
slave_ahb1988
- slave ahb 1988 verilog
ahb_bus
- ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
ahb_verilog_design
- 代码为ahb interface ，用verilog编写的,包括仿真和综合。-Code for the interface AHB, written in Verilog, including simulation and synthesis.
bus_ahb_to_sram
- amba ahb to sram verilog
AMBA
- AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave
abma
- Verilog/VHDL AHB AMBA BUS Arch.
ahb_ebc
- Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
ahb2wishbone_latest.tar
- AHB to wishbone bridge verilog
ahb_sram
- amba总线的ahb到sram的接口，Verilog代码，还算详细，算是不错的资料。(The AHB to SRAM interface of the AMBA bus)
svtb_ahb_sram
- 一款verilog设计的SRAM控制器，可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)